The present invention relates to communications between two circuits. More particularly, the present invention relates to method and system for improving noise margin for a common mode signal in a noise-sensitive receiver circuit.
Some bus communications architectures allow multi-speed data transfers between two or more circuits, devices, or integrated circuit (IC) chips in a computer system or transceiver system. For example, the IEEE 1394 protocol provides such a multi-speed bus architecture. Since the data can be transmitted at a different speed, a receiving circuit should be notified of the data transmission speed in order to properly receive and process the data. One solution is to send a control message specifying the data transmission speed along with transmission of the data. Such a control message is typically attached to the front end of the data transfer, and transmitted concurrently with the data signal. The control message and the data signal may be transmitted using the same communication channel (transmission line) or different channels. Typically, the data signal is conveyed by a differential voltage signal on a pair of differential transmission lines, and the control message is transmitted using a common mode voltage signal.
FIG. 1 schematically illustrates a conventional transmitter-receiver circuit system in which two circuits 10 and 12 communicate. Such circuits may be IC chips such as physical channel interface chip or xe2x80x9cPHYxe2x80x9d chips. The transmitter circuit 10 transmits a data signal (differential signal) and a speed signal (common mode signal) to the circuit 12 over a transmission line 14 having a pair of transmission lines 14a and 14b. In the transmitter circuit 10, the differential data signal is sent from a data transmitter 22, and the common mode signal is generated by a common mode transmitter 24. The common mode transmitter 24 pulls the current (common mode current) on the transmission lines 14a and 14b so as to change the common mode voltage level in accordance with a speed signal to be sent.
At the receiver circuit 12, the signal voltage on the transmission line 14 is input to a differential receiver 15, which extracts the differential data signal therefrom. The respective signal voltages on the transmission lines 14a and 14b are resistively added via resistors 16a and 16b, i.e., averaged to obtain the common mode signal (VCM), which is input to a common mode receiver 18. The resistors 16a and 16b have relatively high impedance, for example, the resistance R1 of 7Kxcexa9. The transmit signal on the transmission line 14 is also resistively coupled to a bias voltage VB. This resistive coupling includes low-impedance resistors 20a and 20b, for example, having resistance R2 of 55xcexa9. The resistors 20a and 20b provide a differential termination of the transmit signal. Also, the resistive coupling via the resistor 20a and 20b provides a reference bias voltage for the common mode signal on the differential transmission lines 14a and 14b. That is, the bias voltage VB is used to set a reference voltage Vref in the common mode receiver 18 to decode the common mode signal.
The common mode receiver 18 includes a comparator for comparing the common mode voltage VCM and the reference voltage Vref. Typically, Vref is set to a predetermined amount xcex94V below the bias voltage VB. Since the differential transmission lines 14a and 14b are biased by the bias voltage VB, existence of the pulling current (i.e., the speed signal) is detected as a voltage drop in the common mode signal from the bias voltage VB.
FIG. 2A schematically illustrates waveforms of the common mode signal 30 (VCM) and the corresponding speed signal 32 (for example, speed signal S200) in a noise free environment. The speed signal S200 indicates the data speed of 200 Megabit per second (Mbps). During the time period where the common mode voltage 30 is below the reference voltage (Vref) 34, the speed signal 32 is asserted, e.g., the speed signal 32 goes high (speed signal phase). The speed signal is then supplied to various digital logic circuits. The data signal is typically transmitted following the speed signal phase (data phase).
However, when there is some noise in the reference voltage Vref, the level of the reference voltage Vref may rise above the bias voltage VB. FIG. 2B schematically illustrates such a case where a bump noise 36 exists in the reference voltage 34. As shown in FIG. 2B, although the common mode voltage 30 returns to the bias voltage level at time t1, the speed signal 32 is still asserted due to the bump noise 36, causing a false speed signal 38. In addition, there may be various noises on the common mode voltage 30 itself, as shown in FIG. 2C. Thus, if the reference voltage 34 becomes too close to the bias voltage level VB due to a bump noise or otherwise, such a noisy common mode voltage may also cause a false speed signal. Such a false signal would hinder proper operation of the digital logic in the receiver circuit.
Furthermore, since the reference voltage Vref is give as VBxe2x88x92xcex94V, and the predetermined voltage amount xcex94V (threshold voltage) is typically specified by a standard or specification, it may be not feasible to change the setting of the reference voltage level in the receiver circuit side. Accordingly, it would be desirable to provide a method and system for improving a noise margin in a noise-sensitive receiver circuit and/or a receiver circuit in a noisy environment without changing the receiver circuit configuration.
A transmitter circuit improves a noise margin for decoding a common mode signal at a receiver circuit. The transmitter circuit includes a common mode signal transmitter and a noise margin enhancement circuit coupled to a transmission line. The common mode signal transmitter transmits a control message using a common mode signal. The common mode signal has a first voltage level and a second voltage level higher than the first voltage level, and the control message corresponds to a portion of the common mode signal having the first voltage level. The noise margin enhancement circuit raises a voltage level of the common mode signal to a third voltage level higher than the second voltage level for a specific time period from a rising edge of the common mode signal from the first voltage level.